Modern ultra-large scale integrated (ULSI) circuits are constructed with up to several millions of active devices, such as transistors and capacitors, formed in a semiconductor substrate. Interconnections between the active devices are created by providing a plurality of conductive interconnection layers, such as polysilicon and metal, which are etched to form conductors for carrying signals between the various active devices. The individual interconnection layers are nominally electrically isolated from one another, and from the silicon substrate, by an insulative interlayer dielectric (ILD), such as silicon dioxide (SiO.sub.2) produced by chemical vapor deposition (CVD). The conductive layers and interlayer dielectric are deposited on the silicon substrate wafer in succession, with each layer being, for example, of the order of 1 micron in thickness. The ILD conformably covers the underlying layer (e.g. a metal layer etched to form conductive interconnects) such that the upper surface of the ILD is characterized by a series of non-planar steps which correspond in height and width to the underlying interconnect lines.
These height variations in the upper surface of the ILD can have deleterious effects on the subsequent steps and layers applied in forming the integrated circuit. For example, a non-planar dielectric surface can interfere with the optical resolution of subsequent photolithographic processing steps. This can make the high resolution lines required for compact ULSI circuits difficult to produce. Additionally, if the height variations in the ILD surface are severe, there is a danger that insufficient metal coverage can occur at the step height variations in the subsequent conductor layer, which can result in open circuit flaws.
In order to combat these difficulties, various techniques have been developed in an attempt to better planarize the upper surface of the ILD. One approach, referred to as chemical-mechanical planarization or polishing (CMP), employs abrasive polishing to remove the surface height variations of the dielectric layer. According to this method the semiconductor wafer is pressed against a moving polishing surface that is wetted with a chemically reactive, abrasive slurry. Slurries are usually either basic or acidic and generally contain a suspension of alumina or silica particles. The polishing surface and wafer are moved relative to one another in an abrasive fashion to remove protruding portions of the dielectric layer. The abrasive polishing process continues until the surface of the ILD is largely flattened.
One problem which has been encountered with subjecting semiconductor wafers to chemical-mechanical polishing is that scratches can be produced on the polished surface of the wafer (e.g. on the surface of the ILD). Metal deposited on the ILD as the next layer of the integrated circuit fills these scratches, but can then be difficult to remove therefrom when forming the metal layer into the desired circuit interconnections. The resulting filaments of metal remaining in the CMP scratches after forming the interconnections can cause a short circuit fault to occur if the scratch is proximate to contacts or interconnection lines in the metal layer.
Thus, what is required is a chemical-mechanical polishing process in which scratches on the wafer surface are avoided or removed prior to deposition of a subsequent conductive layer.